This invention relates to the manufacturing techniques for hybrid semiconductor integrated circuits and structures made in accordance with those techniques.                Hybrid circuits have been widely used in the electronic systems industry for over 40 years. FIG. 1A and FIG. 1B illustrate the basic features of a hybrid circuit. It includes a substrate 101 mounted inside an enclosure or package 103, and the substrate 101 has interconnect traces 105–108 in the substrate 101 and integrated circuit (IC) dies 109, 111 on the substrate 101. The IC dies 109, 111 are glued or otherwise bonded to the substrate 101 using a die attach epoxy and electrically connected to the interconnect traces by means of wire bonds 113, 115 extending from substrate pads 114, 116 on the substrate 101 to die pads 110, 112 on the dies 109, 111. Wire bonds 117 are used to connect the substrate to the package. In addition, wire bonds 119 may be used to connect the IC dies directly to the edge of the package 103. Finally, the package has pins 123 that facilitate the package connection to other packages and printed circuit boards.        
Many variations of the above scheme are practiced which makes hybrid circuit a very versatile methodology for integrating complex systems. For example, the substrate could be made of a printed circuit board, a multi-layer ceramic or a silicon chip with integrated devices such as transistors, resistors and capacitors. The IC die-to-substrate connection (or the substrate-to-package connections) can be formed by many alternate means than wire bonds. Solder balls and flat metal fingers (TABs) are also used for the same purpose. Similarly, the package pins 123 may be formed by solder balls or TABs. In addition to IC die, passive components such as capacitors, inductors, and crystals may be glued onto the substrate and connected to the interconnect traces using wire bonds or other means.
As a general background, reference is made to Rao Tummala, “Fundamentals of Micro-system Packaging,” (McGraw-Hill, 2001.), which summarizes the current state-of-art in hybrid circuit packaging.
The main benefit of hybrid arises from its versatility. One can combine diverse IC functions such as analog, digital, microwave and memories from different sources on a single assembly without incurring the cost and volume of packaging each individual IC die. One can also combine diverse semiconductor technologies in a single assembly such as GaAs, ferro-electric and silicon. In addition the design cost for hybrids is considerably less than that of a comparable single IC solution.
However, there are serious cost issues with hybrids which limit their use to niche markets. The biggest negative is lower yield. Even if a single one of the many ICs on the hybrid fails, it renders the entire hybrid unusable, resulting in low yield and high costs. Removal and replacement of the defective die is expensive, error-prone and time consuming. A further disadvantage is that wire bond (and alternates such as solder ball) connections between IC dies and the substrate are large in comparison with on-chip interconnect technologies. This makes the area of the IC die and the substrate much larger than their single chip counterparts. A still further problem is related to the high cost of inventorying IC dies. In spite of these negatives, hybrids are successfully built and used and are widely employed many electronic systems.
Some hybrid circuits include programmable logic ICs on the substrates. However, such attempts have been intended to provide more flexibility in the functionality of the hybrids and are not directed towards solving the manufacturing issues. In U.S. Pat. No. 6,627,985 entitled “Reconfigurable processor module comprising hybrid stacked integrated circuit die elements” the inventors disclose the use of a field programmable gate array (FPGA) as an IC die. However, it does not teach the use of such programmable logic to improve assembly yield or reduce the cost of inventorying the IC dies. In U.S. Pat. No. 6,614,267 entitled “Electronic circuit device and hybrid integrated circuit with an ASIC and an FPGA” the inventors teach the use of a programmable FPGA die to create a “hybrid integrated circuit in which the specification can quickly be modified and adjusted without preparing a new mask and without compromising the performance of the hybrid integrated circuit”. However, there is no teaching of use of such programmable logic to improve assembly yield or to reduce the cost of inventorying the IC dies. U.S. Pat. No. 5,946,545 entitled “Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit” teaches the use of spare memory chips to repair defective hybrid circuits without costly reassembly. However, the methodology is not applicable to other types of functionalities such as logic. The prior art also does not teach the use of inclusion of redundant logic and I/Os on the IC die to improve yield and lower costs.
What is needed is a mechanism for dealing with potentially defective IC dies that does not require reassembly.